Chip level bias for buffers driving voltages greater than transi

Details Chip level bias for buffers driving voltages greater than transi Chip level bias for buffers driving voltages greater than transi

1997-08-13

1999-10-05

Tokar, Michael

Electronic digital logic circuitry

Significant integrated structure, layout, or layout...

Field-effect transistor

326 81, 326 47, H03K 1900

Patent

active

059630574

ABSTRACT:
An integrated circuit includes a core region and an input-output (I/O) region which has an I/O slot and a voltage supply slot. First and second voltage supply buses and a bias voltage bus extend along the I/O region through the I/O slot and the voltage supply slot. A bias voltage generator is fabricated in the voltage supply slot and is electrically coupled between the first and second voltage supply buses. The bias voltage generator has a bias voltage output which is electrically coupled to the bias voltage bus. A buffer is fabricated in the I/O slot for interfacing with the core region. The buffer includes a bias voltage input which is electrically coupled to the bias voltage bus.

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