Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor
Reexamination Certificate
2002-05-08
2004-01-27
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
Field-effect transistor
C326S047000, C326S102000, C716S030000
Reexamination Certificate
active
06683476
ABSTRACT:
FIELD
This invention relates to the field of integrated circuit design. More particularly, this invention relates to reducing the size and improving the performance of input output cells used in integrated circuits.
BACKGROUND
Input output cells deliver input signals to and carry output signals from integrated circuits, such as ASIC's and ASSP's. The input output cells are typically disposed near a peripheral edge of the integrated circuit, and are connected to bonding pads through which electrical connections are made to other elements of a larger circuit, such as a package for the integrated circuit. Regardless of the actual orientation of the input output cell, the distance between the edge of the input output cell that is nearest its associated bonding pad and the edge of the input output cell that is farthest from its associated bonding pad is typically called the height of the input output cell. The distance between the other two opposing orthogonal edges of the input output cell is typically called the width of the input output cell.
Input output cells are typically electrically connected to two electrical buses, being VDDio and VSSio. In general terms, these two buses comprise the power and ground signals used to power the input output cells. The VDDio and VSSio buses are typically disposed in two concentric rings around the peripheral edge of the integrated circuit. Because the VDDio and VSSio buses typically need to power a large number of input output cells at a high clock rate, the VDDio and VSSio buses are typically quite broad so that they have relatively small ohmic resistances and are relatively resistant to electromigration. The size of the VDDio and VSSio buses also tends to improve the integrated circuit's resistance to electrostatic discharge.
Because the VDDio and VSSio buses are broad in the same direction that the height of the input output cell is measured, and because the input output cell needs to connect to both the VDDio bus and the VSSio bus, the input output cell also tends to be relatively tall. The height of the input output cell also tends to be dictated by the size of the transistors within the input output cell, which are typically fairly large so as to accommodate higher operating voltages and the voltage spikes to which they are often subjected. As the number of devices on the integrated circuit have generally increased, and the overall size of the integrated circuit has generally decreased, the large height of the input output cells has become more of a problem when integrated circuits are laid out, in that they tend to use surface area within the integrated circuit that could more preferably be used for core devices, or eliminated altogether so as to reduce the size of the integrated circuit.
There is a need, therefore, for input output cells that have a reduced height.
SUMMARY
The above and other needs are met by an integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated circuit. The VSSio bus line is disposed along the length and has a second width transverse to the length. The second width of the VSSio bus line substantially overlaps the first width of the VDDio bus line.
An input output cell is disposed on a third layer of the integrated circuit. The first layer, the second layer, and the third layer are all different layers of the integrated circuit. The input output cell has a first transistor electrically connected to the VDDio bus line, and a second transistor electrically connected to the VSSio bus line. The first transistor and the second transistor are disposed along the length within the input output cell.
In this manner, the amount of space on the surface of the integrated circuit typically required for both the first width of the VDDio bus line and the second width of the VSSio bus line is reduced to no more than about the width of the wider of the two bus lines, because the VDDio bus line substantially overlies the VSSio bus line. Further, the first transistor of the input output cell and the second transistor of the input output cell are disposed along the lengths of the VDDio bus line and the VSSio bus line, instead of along the height of the input output cell in a transverse orientation, such as is used in a typical input output cell design. Thus, the height of the input output cell is preferably substantially reduced to be no more than about the width of the greater of the first width of the VDDio bus line and the second width of the VSSio bus line. Thus, an integrated circuit design according to a preferred embodiment of the present invention allows for more surface area of the integrated circuit to be devoted to core components, greatly improving the layout of integrated circuits, especially core limited integrated circuits.
In addition, by overlying the VDDio bus line and the VSSio bus line, electrical noise, such as SSO line noise, is substantially reduced. Thus, additional elements to reduce the electrical noise, which elements required surface area on either the integrated circuit or other components of an external circuit, are no longer needed, and the surface area or other space which they occupied is freed for other purposes.
In various preferred embodiments of the invention, the input output cell has a height that is no greater than about the larger of the first width and the second width, and the input output cell substantially overlies the first width of the VDDio bus line and the second width of the VSSio bus line. In various embodiments, the third layer on which the input output cell resides either overlies both the first layer and the second layer, is disposed between the first layer and the second layer, or is disposed beneath the first layer and the second layer. The first layer may overlie the second layer, or the second layer may overlie the first layer.
Most preferably, an electrical insulation layer is disposed between the first layer and the second layer, forming a plate capacitor for intrinsically decoupling SSO noise on the VDDio bus line and the VSSio bus line. Preferably, a bond pad is electrically connected to the input output cell. The bond pad is preferably disposed between the input output cell and a peripheral edge of the integrated circuit.
REFERENCES:
patent: 6418031 (2002-07-01), Archambeault
Ali Anwar
Lau Tauman T.
Yeung Max M.
Chang Daniel
LSI Logic Corporation
Luedeka Neely & Graham P.C.
LandOfFree
Contact ring architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Contact ring architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Contact ring architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3212380