Circuit for contact pad isolation

Electronic digital logic circuitry – Significant integrated structure – layout – or layout...

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Details

326 49, 326 83, H03K 1900

Patent

active

061148784

ABSTRACT:
A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse or anti-fuse, or even a fusible link which is severed to effect isolation. Additionally, a circuit is provided that switchably isolates one of two contact pads from a logic circuit.

REFERENCES:
patent: 4533841 (1985-08-01), Konishi
patent: 5272365 (1993-12-01), Nakagawa
patent: 5402390 (1995-03-01), Ho et al.
patent: 5517455 (1996-05-01), McClure et al.
patent: 5526317 (1996-06-01), McClur
patent: 5726585 (1998-03-01), Kim
patent: 5859442 (1999-01-01), Manning
patent: 5929691 (1999-07-01), Kim et al.

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