Clock driver circuit in a centrally located macro cell layout re

Details Clock driver circuit in a centrally located macro cell layout re Clock driver circuit in a centrally located macro cell layout re

1997-06-02

1999-08-31

Tokar, Michael

Electronic digital logic circuitry

Significant integrated structure, layout, or layout...

326 47, 326 93, 327295, 257206, 257207, H03K 1901, H01L 2710

Patent

active

059458461

ABSTRACT:
A clock driver circuit is furnished in a centrally located macro cell layout region. The clock driver circuit has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a first and a second common line, and the input and output nodes of the main drivers are short-circuited by the second and a third common line. A plurality of clock driver circuits are formed predetermined distances apart and arranged to intersect the clock driver circuit perpendicularly. Each of the clock driver circuits has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a fourth and a fifth common line, and the input and output nodes of the main drivers are short-circuited by the fifth and a sixth common line. The third and the fourth common lines are interconnected. The sixth common line is connected to clock signal supply lines which in turn are connected to a plurality of second macro cells.

REFERENCES:
patent: 5270592 (1993-12-01), Takahashi et al.
patent: 5298774 (1994-03-01), Ueda et al.
patent: 5430397 (1995-07-01), Itoh et al.
patent: 5444276 (1995-08-01), Yokota et al.
patent: 5519351 (1996-05-01), Matsumoto
patent: 5608484 (1997-03-01), Nomura
patent: 5773855 (1998-06-01), Colwell et al.

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