Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor
Reexamination Certificate
1998-03-30
2001-05-08
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
Field-effect transistor
C326S083000, C326S121000, C257S351000
Reexamination Certificate
active
06229342
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to circuits and methods for body contacted and backgated transistors.
BACKGROUND OF THE INVENTION
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever increasing number of linked transistors. As the number of transistors required increases, the surface area that can be dedicated to a single transistor dwindles. It is desirable then, to construct transistors which occupy less surface area on the silicon chip/die.
Integrated circuit technology uses transistors conjunctively with Boolean algebra to create a myriad of functional digital circuits, also referred to as logic circuits. In a typical arrangement, transistors are combined to switch or alternate an output voltage between just two significant voltage levels, labeled logic 0 and logic 1. Most logic systems use positive logic, in which logic 0 is represented by zero volts, or a low voltage, e.g., below 0.5 V; and logic 1 is represented by a higher voltage.
One method in which these results are achieved involves Complementary Metal-Oxide Semiconductor (CMOS) technology. CMOS technology comprises a combination of oppositely doped Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs) to achieve the switching mechanism between voltage levels associated with logic 0 and that of logic 1. This configuration is likewise referred to as an inverter. Conventional CMOS inverters consume an appreciable amount of chip surface area, even despite ongoing reductions in the critical dimensions that are achievable with conventional photolithography techniques. The critical dimension (F) represents the minimum lithographic feature size that is imposed by lithographic processes used during fabrication. It is one objective, then, to fabricate CMOS inverters which conserve silicon chip surface space
Standby current is another significant concern and problem in low voltage and low power battery operated CMOS circuits and systems. High threshold voltage transistors and high power supply voltages were traditionally employed in part to minimize subthreshold leakage at standby. Today, however, low voltages are desired for low power operation and this creates a problem with threshold voltages and standby leakage current. In order to get significant overdrive and reasonable switching speeds the threshold voltage (V
t
) magnitudes must be small, e.g. zero volts. However, having such low threshold voltages generally causes one of the transistors to have a large subthreshold leakage current. Various techniques have been employed to allow low voltage operation with CMOS transistors and maintain low subthreshold leakage currents at standby.
Dynamic CMOS circuits achieve this objective using clock or phase voltages to turn off conduction from the power supply to ground through the chain of devices when the inverter is at standby. Synchronous body bias has similarly been employed in part to minimize subthreshold leakage. However, synchronous body bias, like dynamic logic, requires extra clock or phase voltage lines throughout the circuit. This increases considerably the complexity of circuits and consumes precious space on the chip. Also, data stored only on a dynamic basis must be clocked and refreshed.
Another way to get around these problems involves implementing resistors to provide a source to substrate bias or backgate bias when the transistor is in the off state or, in other words, to create a “switched source impedance.” The problem with this method is that resistors are troublesome to fabricate in CMOS process steps.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need to develop improved inverter devices. The devices should desirably minimize subthreshold leakage current and conserve chip surface space while continuing to advance the operation speeds in logic circuits. The improved inverter circuits and structures should remain fully integral with CMOS processing techniques.
SUMMARY OF THE INVENTION
The above mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A circuit and method is provided to minimize subthreshold leakage currents at standby in low power CMOS circuits and systems.
In particular, an illustrative embodiment of the present invention includes an inverter. The inverter includes a first, second, third, and fourth transistor. Each of the transistors extends outwardly from a semiconductor substrate. Each of the four transistors has an upper surface and opposing sidewall surfaces. Each of the transistors includes a source/emitter region, a body/base region, and a collector/drain region. An electrical contact couples between the collector/drain regions of the second and third transistors to provide an output for the inverter. A gate contact interconnects the four transistors and provides an input to the inverter.
In another embodiment, a logic circuit is provided. The logic circuit includes multiple inverters that form an array. Each of the inverters includes a first, second, third, and fourth transistor. Each of the four transistors has an upper surface and opposing sidewall surfaces. Each of the transistors include a source/emitter region, a body/base region, and a collector/drain region. An electrical contact couples between the collector/drain regions of the second and third transistors to provide an output for the inverter. A gate contact connects the four transistors and provides an input to the inverter. A metallization layer selectively interconnects the inputs and outputs of the inverters to implement a logic function. The logic circuit accepts inputs and produces one or more logical outputs.
In another embodiment, an input/output device is provided. The input/output device includes a functional circuit that has a plurality of components. A logic device is coupled to the functional circuit. The logic device has a number of inverters and each inverter has a first, second, third, and fourth transistor. Each of the transistors extends outwardly from a semiconductor substrate. Each of the four transistors has an upper surface and opposing sidewall surfaces. Each of the transistors includes a source/emitter region, a body/base region, and a collector/drain region. An electrical contact couples between the collector/drain regions of the second and third transistors to provide an output for the inverter. A gate contact connects the four transistors and provides an input to the inverter. A metallization layer is also provided that selectively interconnects the inputs and outputs of the inverters to form a logic circuit that accepts inputs and produces one or more logical outputs.
In another embodiment, a method of fabricating an inverter is provided. The method includes forming a first, second, third, and fourth transistor. The four transistors are formed to extend outwardly from a semiconductor substrate. The transistors are each formed with an upper surface and opposing sidewall surfaces. The transistors are formed to include a source/emitter region, a body/base region, and a collector/drain region. An electrical contact is formed between collector/drain regions of the second and third transistors to provide an output for the inverter. A gate contact is formed which interconnects the transistors. The gate contact provides an input to the inverter.
In another embodiment, a method of fabricating an array of inverters is provided. The method includes forming multiple inverters such that each of the inverters is formed as described above. A metallization layer is formed that selectively interconnects the inputs and outputs of the inverters to form a logic circuit. The logic circuit accepts inputs and produces one or more logical outputs.
Thu
Forbes Leonard
Noble Wendell P.
Cho James A
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Tokar Michael
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