Gatable level-pulling circuit

Details Gatable level-pulling circuit Gatable level-pulling circuit

1995-10-13

1997-01-14

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 86, H03K 190175

Patent

active

055943624

ABSTRACT:
Integrated circuit components automatically establish or disable a level-pulling condition relative to a given input IC pin as a function of detected signal activity at such IC pin, A logic signal responsive to signal activity at the IC pin drives the gate of a field effect transistor (FET) to dynamically establish or disable level-pulling function at the IC pin. Alternative embodiments include a flop-flop register and an OR gate driving the gate of the FET.

REFERENCES:
patent: 5051622 (1991-09-01), Pleva
patent: 5111079 (1992-05-01), Steele
patent: 5432465 (1995-07-01), Hsi-Jung et al.

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