Gate array cell with predefined connection patterns

Details Gate array cell with predefined connection patterns Gate array cell with predefined connection patterns

1994-01-10

1995-02-21

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

257203, 326121, 326 37, 326 50, 327566, H03K 19017

Patent

active

053919432

ABSTRACT:
A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10 and a plurality of P-channel transistors 12. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional N-channel (14) and P-channel (70, 72) transistors are included in the base cell at least some of which are larger in size than those in the plurality of N-channel transistors 10 or the plurality of P-channel transistors 12. These larger size transistors are used as output drivers to send the logical output signal of the cell to another cell.

REFERENCES:
patent: 4682202 (1987-07-01), Tamizawa
patent: 4727266 (1988-02-01), Fujii et al.
patent: 4978633 (1990-12-01), Seefeldt et al.

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