Gate array cell with predefined connection patterns

Details Gate array cell with predefined connection patterns Gate array cell with predefined connection patterns

1995-04-28

1996-03-26

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Field-effect transistor

326 41, 326 45, H01L 2500, H03K 19173

Patent

active

055024041

ABSTRACT:
A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10, 12, 14 with all such N-channel transistors coupled in series. A plurality of P-channel transistors 16, 18 coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Specifically, the gates of two of the N-channel transistors 12, 14 are connected by polysilicon lead 28 to the gate of transistor 16. This configuration forms a circuit primitive which is well adapted for use as a base cell in a programmable array device.

REFERENCES:
patent: 4745307 (1988-05-01), Kitamura
patent: 4771327 (1988-09-01), Usui
patent: 4785199 (1988-11-01), Kolodny
patent: 5055716 (1991-10-01), El Gamal
patent: 5391943 (1995-02-01), Mahant-Shetti
patent: 5422581 (1995-06-01), Mahant-Shetti
patent: 5428255 (1995-06-01), Wall

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