Method, apparatus and system of domino multiplexing
Methodology to test pulsed logic circuits in pseudo-static mode
Methods and apparatus for bipolar elimination in silicon-on-insu
Methods and apparatus for fast unbalanced pipeline architecture
Methods and apparatus for providing a negative delay on an IC ch
Methods and apparatus for serially connected devices
Methods and arrangements for an enhanced scanable latch circuit
Methods and arrangements for enhancing domino logic
Midcycle latch for power saving and switching reduction
Modified charge recycling differential logic
Modified domino logic circuit with high input noise rejection
Modular buffering circuitry for multi-channel transceiver...
Monotonic dynamic static pseudo-NMOS logic circuits
Monotonic dynamic static pseudo-NMOS logic circuits
Monotonic dynamic-static pseudo-NMOS logic circuit
Monotonic leakage-tolerant logic circuits
Multi-input transition detector with a single delay
Multiple supply voltage dynamic logic
Multiple supply-voltage zipper CMOS logic family with low...
Multiport arbitration using phased locking arbiters