Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2001-12-20
2004-02-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S097000, C326S098000
Reexamination Certificate
active
06693461
ABSTRACT:
FIELD
Embodiments of the present invention relate to digital circuits, and more particularly, to dynamic (domino) circuits with reduced leakage current.
BACKGROUND
As integrated circuit process technology allows for smaller and smaller device size, active leakage power dissipation may become a significant component of the total energy dissipated during normal activity. Active leakage power dissipation results when sub-threshold leakage current in a transistor flows across a voltage drop. An example of sub-threshold leakage current is source-to-drain current in a nMOSFET (Metal-Semiconductor-Field-Effect-Transistor) when its gate-to-source voltage is less than its threshold voltage. This active leakage power dissipation not only contributes to unwanted total energy dissipation, but it also affects the performance of dynamic circuits.
A prior art zipper domino circuit is illustrated in FIG.
1
. For simplicity, the circuit of
FIG. 1
comprises four dynamic stages, where n-logic
102
and n-logic
104
each comprise one or more nMOSFETs connected in various serial and parallel combinations, and p-logic
106
and p-logic
108
each comprise one or more pMOSFETs connected in various serial and parallel combinations, so as to achieve the overall desired logic function for the circuit. For simplicity, only one input port to n-logic
102
, denoted as port
110
, is shown, but in practice there may be a plurality of such input ports. Also for simplicity, only one input port is shown for each of the other dynamic stages, connected to the output port of the previous dynamic stage, but in practice there may be a plurality of input ports to each of the dynamic stages, perhaps being fed by other circuits, dynamic or static. In
FIG. 1
, V
CC
denotes a nominal supply voltage, and V
SS
denotes a substrate (or ground) voltage.
The clock signal is denoted as &phgr;, and its Boolean (logical) complement by {overscore (&phgr;)}. Each stage has a pre-charge phase and an evaluation phase, where clock signal&phgr; is HIGH during an evaluation phase and is LOW during a pre-charge phase. During a pre-charge phase pulldown nMOSFET
112
is OFF and pullup pMOSFET
114
is ON to charge node
116
by providing a low impedance path between node
116
and power rail
118
at supply voltage V
CC
. Also during a pre-charge phase, pullup pMOSFET
120
is OFF and pulldown nMOSFET
122
is ON to discharge node
124
by providing a low impedance path between node
124
and ground (substrate)
126
. Similar remarks apply to the other dynamic stages during a pre-charge phase. Note that during a pre-charge phase, node
124
is being discharged rather than charged, so that a p-logic stage may be referred to as having a pre-discharge phase. For simplicity of terminology, it is to be understood that the term “pre-charge” will also refer to “pre-discharge”.
During an evaluation phase, clock signal &phgr; is HIGH so that pMOSFET
114
is OFF and nMOSFET
112
is ON, so that the combination of n-logic
102
and nMOSFET
112
conditionally provide a low impedance path between node
116
and ground (substrate)
126
depending upon the input voltages to n-logic
102
. If a low impedance path is so provided, node
116
is discharged. Otherwise, the half-keeper comprising pMOSFET
128
and inverter
130
maintains node
116
in a charged state. Other n-logic dynamic stages operate in similar fashion.
During an evaluation phase, nMOSFET
122
is OFF and pMOSFET
120
is ON, so that the combination of p-logic
106
and pMOSFET
120
conditionally provide a low impedance path between node
124
and power rail
118
depending upon the input voltages to p-logic
106
. If a low impedance path is so provided, node
124
is charged. Otherwise, the half-keeper comprising nMOSFET
132
and inverter
134
maintains node
124
in a discharged state. Other p-logic dynamic stages operate in similar fashion.
Note that during a pre-charge phase, nodes in n-logic stages that feed into input ports of p-logic stages are HIGH so that the p-logic stages are OFF. Also note that during a pre-charge phase, nodes in p-logic stages that feed into input ports of n-logic stages are LOW so that n-logic stages not on a clock boundary are OFF. Consequently, the pullup pMOSFETs to p-logic stages and the pulldown nMOSFETs to n-logic stages not on a clock boundary may be removed with connections made directly to power rail
118
or ground
126
, as appropriate, provided the other input ports to the p-logic stages are held HIGH and the other input ports to the n-logic stages are held LOW. This is the reason for using dashed lines for various pullup pMOSFETs and pulldown nMOSFETs.
Sub-threshold leakage current in the n-logic and p-logic stages may cause unwanted power dissipation, reduced noise robustness, as well as slower performance. For example, leakage current may cause a node that is suppose to be held HIGH to drop to a low enough voltage so that the circuit does not evaluate properly. One approach to maintaining noise robustness is to upsize the half-keeper circuits so that the various internal nodes are maintained at their proper states. However, this may increase circuit delay because of possible contention between half-keepers and the n-logic or p-logic.
Another approach to mitigating the effects of sub-threshold leakage current is to utilize high threshold voltage devices in the n-logic and p-logic. However, using high threshold voltage devices may decrease circuit performance.
REFERENCES:
patent: 5525916 (1996-06-01), Gu et al.
patent: 5973514 (1999-10-01), Kuo et al.
patent: 6002272 (1999-12-01), Somasekhar et al.
patent: 6255853 (2001-07-01), Houston
Hsu Steven K.
Krishnamurthy Ram
Kalson Seth Z.
Tokar Michael
Tran Anh Q
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