Midcycle latch for power saving and switching reduction

Details Midcycle latch for power saving and switching reduction Midcycle latch for power saving and switching reduction

2007-05-29

2007-05-29

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S097000, C326S098000

Reexamination Certificate

active

11009830

ABSTRACT:
The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit comprising a precharge node at the input of said logic function implementation, an output latch connected to the output node of said logic function for stabilizing the result of the evaluation of said logic function. The present invention provides such integrated dynamic circuit with a latch, which is protected against instability even in situations involving complex logic functions which are evaluated and their output states are saved by said output latch.

REFERENCES:
patent: 5796282 (1998-08-01), Sprague et al.
patent: 5841304 (1998-11-01), Tam
Monotoye et al., “A Double precision Floating Point Multiplier”, ISSCC 2003, vol. 46, pp. 336, Digest of technical papers, Visuals Supplement, pp. 270, no month.

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