Methodology to test pulsed logic circuits in pseudo-static mode

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates

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326 16, 326 21, 326 40, 371 225, H03K 19003

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active

057480125

ABSTRACT:
A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test the circuit in a pseudo-static mode of operation.

REFERENCES:
patent: 5543731 (1996-08-01), Sigal et al.
patent: 5543735 (1996-08-01), Lo
patent: 5557620 (1996-09-01), Miller, Jr. et al.
patent: 5565798 (1996-10-01), Durham et al.

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