Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2007-02-27
2007-02-27
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S093000, C326S112000
Reexamination Certificate
active
10879260
ABSTRACT:
Embodiments of the present invention provide a method, apparatus and system for domino multiplexing including sustaining a first domino block output in a preconditioning state using a second domino block output.
REFERENCES:
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 5382844 (1995-01-01), Knauer
patent: 6163173 (2000-12-01), Storino et al.
patent: 6437602 (2002-08-01), Friend et al.
patent: 6690204 (2004-02-01), Belluomini et al.
Principles of CMOS VLSI Design, by Nell Weste & Kamran Eshraghla: Chapter 5, pp. 308-309: CMOS Circuit and Logic Design: “5.4.7 CMOS Domino Logic”, no date.
“The Implementation of the Itanium 2 Microprocessor” IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, Samuel D. Naffziger et al., pp. 1448-1460.
Persun Marijan
Seal Chayan Kumar
Chang Daniel
Intel Corporation
Pearl Cohen Zedek Latzer LLP
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