Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2008-03-31
2010-02-23
Chang, Daniel D (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S046000, C377S064000, C377S069000
Reexamination Certificate
active
07667494
ABSTRACT:
Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time.
REFERENCES:
patent: 4630295 (1986-12-01), Kamuro et al.
patent: 08265168 (1996-10-01), None
Andreev Alexander
Pavisic Ivan
Vikhliantsev Igor
Chang Daniel D
LSI Corporation
Ryan & Mason & Lewis, LLP
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