Modified domino logic circuit with high input noise rejection

Details Modified domino logic circuit with high input noise rejection Modified domino logic circuit with high input noise rejection

2000-06-08

2002-03-05

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S093000

Reexamination Certificate

active

06353339

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to digital circuits and, more particularly, to domino logic circuits. Still more particularly, the present invention relates to modified domino logic circuits with increased noise tolerances.
BACKGROUND OF THE INVENTION
Domino logic circuits are well known to those of skill in the art.
FIG. 1A
schematically illustrates a generalized prior art domino logic circuit
100
A which typically included: supply voltage VDD; P-channel transistor
122
; logic block
110
, with data input nodes IN
1
to INN; inverter
130
; N-channel transistor
105
; and ground supply voltage VSS.
In generalized prior art domino logic circuit
100
A, source
122
S of P-channel transistor
122
was coupled to junction
181
and supply voltage VDD. Gate
122
G of P-channel transistor
122
was connected to node
142
which received clock signal CK. Drain
122
D of P-channel transistor
122
was connected to junction
183
. Node
183
was connected to a first internal node
190
and node
111
of logic block
110
. First internal node
190
was also connected to input node
132
of inverter
130
. Inverter
130
included output node
133
that was coupled to circuit output node
135
.
Logic block
110
typically comprised one of several different logic circuits and/or gates well known to those of skill in the art. For instance, in one embodiment, logic block
110
comprised AND gate logic. However, logic block
110
could also comprise a NAND gate, OR gate, NOR gate, selective OR gate or any other gate or logic circuit required for a particular application of generalized prior art domino logic circuit
100
A. Input nodes IN
1
to INN of logic block
110
were connected to receive data signals D
1
to DN. The number of data signals “DN”, and therefore the number in input nodes “INN” varied depending on the logic making up a particular embodiment of logic block
110
and the requirements of the system (not shown) employing prior art domino logic circuit
100
A. A specific embodiment of logic block
110
is discussed in more detail below.
Logic block
110
also included node
112
that was connected to a second internal node
187
. Second internal node
187
was connected to drain
105
D of N-channel transistor
105
. Gate
105
G of N-channel transistor
105
was connected to input node
144
to receive the clock signal CK. Source
105
S of N-channel transistor
105
was then connected to junction
189
and ground supply voltage VSS.
FIG. 1B
schematically illustrates a prior art domino logic circuit
100
B. Prior art domino logic circuit
100
B is one of several possible embodiments of generalized prior art domino logic circuit
100
A discussed above. Consequently, prior art domino logic circuit
100
B is identical to generalized prior art logic circuit
100
A but includes an AND gate embodiment of logic block
110
which comprises two data inputs, D
1
and D
2
, and two N-channel transistors
101
and
103
.
Prior art domino logic circuit
100
B typically received two input data signals D
1
and D
2
at nodes
150
and
160
, respectively. Prior art domino logic circuit
100
B, like generalized prior art domino logic circuit
100
A, also typically included P-channel transistor
122
and N-channel transistor
105
.
As shown in
FIG. 1B
, N-channel transistors
101
and
103
were typically NMOS transistors having their channel regions connected in series between the drain
122
D of P-channel transistor
122
at junction
183
and the drain
105
D of N-channel transistor
105
at second internal node
187
. More specifically, the source
122
S of P-channel transistor
122
was connected to supply voltage VDD at junction
181
and the drain
122
D of P-channel transistor
122
was connected to junction
183
, first internal node
190
, and input node
132
of inverter
130
. Inverter
130
also included output node
133
connected to circuit output node
135
.
N-channel transistor
101
typically had its drain
101
D connected to junction
183
that, as discussed above, was connected to drain
122
D of P-channel transistor
122
, first internal node
190
, and input node
132
of inverter
130
. Source
101
S of N-channel transistor
101
was connected to the drain
103
D of N-channel transistor
103
at junction
185
. The source
103
S of N-channel transistor
103
was connected to drain
105
D of N-channel transistor
105
at second internal node
187
. The source
105
S of N-channel transistor
105
was connected to ground supply voltage VSS at junction
189
.
As with generalized prior art domino logic circuit
100
A discussed above, in prior art domino logic circuit
100
B, gate
122
G of P-channel transistor
122
and gate
105
G of N-channel transistor
105
were connected to nodes
142
and
144
, respectively, to receive the clock signal CK. In addition, gate
101
G of N-channel transistor
101
was connected to node
150
to receive data signal D
1
and gate
103
G of N-channel transistor
103
was connected to node
160
to receive data signal D
2
.
Particular types of transistors are discussed above, made by particular processes and with particular first or second channel types, i.e., “P” or “N” channel types. However, those of skill in the art will readily recognize that other types of transistors, made by other processes and/or having opposite first and second channel types, could be employed by making minor modifications such as changing the supply voltages VSS and VDD. The choice of the particular transistor types for the discussion above was made for exemplary purposes only. Therefore, this choice of transistor types should not be read as limiting the discussion of the prior art, or the invention, to the particular embodiments shown.
Disadvantageously, prior art domino logic circuits
101
A and
100
B were very sensitive, and therefore susceptible to, input noise levels on signals D
1
to DN. Consequently, an input noise peak larger in magnitude than the threshold voltage of the evaluation device could, and often would, trigger domino logic circuit
100
A or
100
B and cause a logic malfunction. This was primarily because prior art domino logic circuits
100
A and
100
B did not use complementary logic so there was no buffer or “fight” with a complementary component during evaluation. Consequently, first internal node
190
of prior art domino logic circuits
100
A and
100
B started discharging as soon as the level of input signal D
1
to DN went slightly above the threshold voltage of the pull down (or pull up) device, i.e., N-channel transistors
101
and
103
in FIG.
1
B.
For instance, referring to
FIG. 1B
, assume data signal D
1
at node
150
was high, i.e., a logic “
1
”, during evaluation, i.e., when clock signal CK was a high. In this case, first internal node
190
would start discharging when data signal D
2
at node
160
reached the threshold voltage of N-channel transistor
103
(VTH
103
). Assuming that clock signal CK was high prior to signal D
2
reaching VTH
103
, second internal node
187
, i.e., source
103
S of N-channel transistor
103
was at the same voltage as the ground supply voltage VSS. Therefore, the threshold voltage of N-channel transistor
103
was the threshold specified at zero bias voltage, i.e., VTH
103
, assuming no body effect. Consequently, prior art domino logic circuits
100
A and
100
B were very sensitive and susceptible to input noise levels and suffered from poor noise rejection characteristics and a low noise threshold.
Since prior art domino logic circuits
100
A and
100
B were so sensitive and susceptible to input noise levels, in prior art systems where input noise levels could not be reduced by other means static buffers were added to the inputs of dynamic domino logic circuits, such as prior art domino logic circuits
101
A and
100
B. The addition of these static buffers (not shown) created a static domino logic circuit (not shown) that was less vulnerable to noise. However, using this prior art buffer method, at least four additional devices (not shown) were required for each stati

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