Methods and apparatus for bipolar elimination in silicon-on-insu

Details Methods and apparatus for bipolar elimination in silicon-on-insu Methods and apparatus for bipolar elimination in silicon-on-insu

1999-03-16

2000-07-25

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 15, 326119, H03K 19096, H03K 19094, H03K 1920, H03K 19003

Patent

active

060940727

ABSTRACT:
In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. Apparatus for bipolar elimination in silcon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect transistor. An input is coupled to the domino silicon-n-insulator (SOI) field effect transistor. A predischarging device is coupled to said domino silicon-on-insulator (SOI) field effect transistor. The predischarging device is activated during a precharge mode of the domino circuit, so that the SOI parasitic bipolar transistor is not activated. A dynamic input circuit couples the input to the domino silicon-on-insulator (SOI) field effect transistor. The output of the dynamic input circuit is low during the precharge mode. The output of the dynamic input circuit corresponds to the input during the evaluate mode. The output of the dynamic input circuit is used to gate the predischarging device.

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Research Disclosure, "Pre-Discharge Technique to Improve Noise Immunity on Silicon-on-Insulator (SOI) Domino Circuits", by Anonymous, Apr. 1998, pp. 496-497.

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