Signal-initiated power management method for a pipelined...

Simultaneous multi-threading processor circuits and computer...

Single chip clock control circuit operating independently of CPU

Single chip integrated circuit with external bus interface

Single chip microcomputer with reduced channel leakage...

Single wire network for sending data in predetermined...

Skipping clock interrupts during system inactivity to reduce pow

Sleep mode indicator for a battery-operated device

Sleep mode transition between processors sharing an...

Sleepmode activation in a slave device

Slew rate limited reference for a buck converter

Smart battery power management in a computer system

Smart batteryless backup device and method therefor

Smart DASD spin-up

SMBUS over the PCI bus isolation scheme and circuit design

SMM power management circuits, systems, and methods

SOC with low power and performance modes

Software control of transistor body bias in controlling chip...

Software processing apparatus with a switching processing...

Software-based sleep control of operating system directed...