Sleepmode activation in a slave device

Details Sleepmode activation in a slave device Sleepmode activation in a slave device

1999-04-28

2002-05-21

Heckler, Thomas M. (Department: 2182)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S601000

Reexamination Certificate

active

06393572

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of digital systems, and in particular to computer systems that employ primary and secondary, or master and slave, device configurations.
2. Description of Related Art
Parallel processing is often used to accomplish a variety of simultaneous tasks within a computing system. Special purpose devices, such as math coprocessors, audio and video coprocessors, and the like are often used to off-load tasks from the main processor to allow the main processor to perform other tasks while the special purpose devices are simultaneously performing the offloaded tasks.
A common offloaded task is the coding and decoding of audio information, using an Audio Codec (COder-DECoder), typified for example, by a device that conforms to the “Audio Codec '97 Rev 2.1” specification from Intel Corporation (Reference 1). The fundamental task of an audio codec is to accept digitally encoded information from a processor and provide a corresponding analog audio signal to a speaker or headset, and to accept analog audio information from a microphone and provide digitally encoded information to the processing system.
Because of the increasing demand for multimedia capabilities, the use of multiple codecs within a computer system is becoming increasingly common. The architecture of a multiple codec configuration in the referenced AC '97 specification is similar to that used for other configurations of multiple-instance devices. To ease interconnection logistics, the multiple codecs are configured to operate in parallel with each other, as illustrated in FIG.
1
.
FIG. 1
illustrates an AC'97 digital controller
110
and three codecs
121
-
123
. To ease the synchronization and control demands on the computer system, one of the multiple codecs
121
is designated as the primary, or master, codec, and each of the other codecs
122
,
123
are designated as secondary, or slave, codecs. The unique identification of each codec
121
-
123
is effected via the values associated with each codec's identifier bits ID
0
and ID
1
; having two identification bits allows for up to four codecs to be uniquely identifiable. Other multiple-device systems may use more or fewer bits to accommodate more or fewer multiple instances. In a typical AC'97 configuration, the codecs are assigned unique identifiers via external pins that are tied to a logic 0 bus
140
or a logic 1 bus
141
. As illustrated in
FIG. 1
, the identification bits ID
0
and ID
1
of the primary codec
121
are tied to the logic 0 bus
140
, and therefore the identification, or address, of the primary codec
121
is “00”. In like manner the addresses of codecs
122
and
123
are “01” and “10”, respectively. As is common in the art, the polarity of the identification bits may be reversed; the specific values presented herein are for illustrative purposes only.
The digital controller
110
of
FIG. 1
has a single data output port SDATA_OUT
132
that is communicated to each of codecs
121
-
123
in parallel. The digital controller uses the aforementioned unique address of each codec to route the appropriate information, or frame of data, to the appropriate codec.
FIG. 2
illustrates an example prior art codec
120
(of which the codecs
121
-
123
are instances) that is configured to operate in a multiple-codec configuration. Illustrated in
FIG. 2
is an input frame buffer
210
that receives each frame of data from the controller
110
(not shown in
FIG. 2
) via SDATA_OUT
132
. Each frame of data includes an address field
212
and a command field
214
that identify the device for which the frame is intended, and the action required of the device. Not illustrated, each frame typically also contains data bits and ancillary bits, such as control bits, error field bits, status bits, and the like.
The codec
120
includes an address detector
220
that determines whether it is the intended recipient of the frame of data, by comparing the address field
212
of the frame to the logic values assigned to the identification bits ID
0
200
and ID
1
201
of the particular instance of the codec
120
. If the address field
212
matches the identification bits
200
,
201
, the chip select signal
221
is asserted. When the chip select signal
221
is asserted, the command processor
230
processes the command
214
and communicates the appropriate commands and parameters for the signal processor
240
to effect the command
214
. If the chip select signal
221
is not asserted, the command processor ignores the command
214
and the signal processor
240
is free to continue, uninterrupted, any remaining processing from prior commands that were addressed to this codec. In this manner, each codec
121
-
123
is provided time to perform their primary signal processing function while devoting minimal time to the processing of unrelated frame data that is received via the common SDATA_OUT
132
.
Illustrated in
FIG. 2
is a sleep, or power-down, circuit
290
. Upon receipt of a sleep command
214
addressed to the particular device
120
, the device
120
is placed into a mode that consumes minimal power. Using techniques common in the art, the sleep circuit
290
includes the control logic required to assure that the nodes in the device
120
are placed in a low power consuming state, and, if required, includes the control logic required to store any data that is required to be preserved until the device
120
is again awakened into an active, higher power, mode. Typically, the power-down of a device is a multi-step process; conventionally, the sleep circuit
290
includes sequential devices, and the clocking signal
131
provides the required clocking signaling for these devices, and other sequential devices within the device
120
, as required.
In a typical master-slave configuration, the master device is often responsible for tasks that are common to all the devices. For example, a task of a typical AC'97 codec is to provide the clocking signal BIT_CLK
131
for communicating with the controller
110
. In an AC '97 multiple-codec configuration, the primary codec
121
is tasked to provide the clocking signal
131
as an output, and each of the secondary codecs
122
-
123
must accept this clocking signal as an input. This common clocking signal is typically employed to assure the synchronization of a controller and each of the master and slave devices.
Because the master device provides the clocking signal, however, a power-down of the master device ceases the clocking signal to each of the slave devices, and this cessation can have an adverse effect on the subsequent operation of the slave devices, particularly if the slave devices contain dynamic memory that must be periodically refreshed to retain their state. The cessation of the clocking signal can also have an adverse effect on the effectiveness of the power-down, or sleepmode, operation by leaving nodes in potentially power consuming states.
To effect a controlled power-down after the cessation of the clock, the slave device must be aware that the clock has stopped, and must thereafter effect the appropriate actions to save any required memory contents and to assure that all nodes are in a minimal power consumption state.
FIG. 2
illustrates the conventional use of a clock cessation detector
260
to effect a controlled power-down after the BIT_CLK
131
ceases its transitions. Analog circuitry, such as a “one-shot” timing circuit, may be employed in the clock cessation detector
260
to detect an absence of the clock signaling
131
after a predetermined time period. Alternatively, an auxiliary clock generator
250
is often provided for generating an auxiliary clocking signal
231
that is used to detect the absence of the clocking signal
131
using digital circuitry. Typically, the auxiliary clock generator
250
is a crystal driven circuit that requires that an external crystal, thereby increasing the system cost and complexity. Because the power-down of a device is usually a

Affiliated with

Also associated with

Rating

Sleepmode activation in a slave device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sleepmode activation in a slave device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sleepmode activation in a slave device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2879344