Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2000-11-28
2004-07-13
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S322000
Reexamination Certificate
active
06763471
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a single chip microcomputer suitably used for an electronic device such as a video camera or the like operated at a plurality of speeds. More particularly, the invention relates to a single chip microcomputer capable of reducing power consumption.
2. Description of the Related Art
A conventional single chip microcomputer comprises two kinds of oscillators provided to generate high-speed and low-speed clock signals, respectively. During a high-speed operation, a central processing unit (referred to as a CPU, hereinafter) is operated by a high-speed clock signal. During a low-speed operation, the CPU is operated by a low-speed clock signal.
FIG. 1
is a block diagram showing the constitution of such a conventional single chip microcomputer.
The conventional single chip microcomputer shown comprises first and second oscillators
103
and
104
, to which power supply voltage Vdd is supplied from a power supply terminal. An oscillation frequency of the first oscillator
103
is set equal to, e.g., 20 MHz, while an oscillation frequency of the second oscillator
104
is set equal to, e.g., 32 kHz. In other words, the first oscillator
103
is designed for a high-speed clock signal, whereas the second oscillator
104
is designed for a low-speed clock signal.
The single chip microcomputer also comprises a selector
105
which is provided to select each of the clock signals G
5
and G
6
of the first and second oscillators
103
and
104
, and output it as a clock signal G
4
to a CPU
110
. The microcomputer further comprises a random access memory (referred to as a RAM, hereinafter)
106
, a read only memory (referred to as a ROM, hereinafter)
107
, and a peripheral circuit
108
. An I/O port
111
is also provided to transfer a signal with an external unit, and with the CPU
110
for transferring a signal with the CPU
110
.
In addition, a control circuit
112
is provided to control an oscillation frequency of a clock signal inputted to the CPU
110
based on a switching signal A
1
outputted therefrom The control circuit
112
outputs an oscillator control signal G
1
to the first oscillator
103
, where the control signal G
1
is used to switch the operation of the first oscillator
103
between ON and OFF. The control circuit
112
outputs an oscillator control signal G
2
to the Second oscillator
104
, where the control signal G
2
is used to switch the operation of the second oscillator
104
between ON and OFF. On the other hand, the clock signals G
5
and G
6
are inputted not only to the selector
105
but also to the control circuit
112
. To the selector
105
, the control circuit
112
outputs a clock selection signal G
3
used to control the selection of the clock signals G
5
and G
6
.
The power supply terminal directly supplies power supply voltage Vdd to the RAM
106
, the ROM
107
, the peripheral circuit
108
, the CPU
110
, the I/O port
111
and the control circuit
112
.
In addition, a reset signal RST is inputted to each of the CPU
110
and the control circuit
112
to realize its initial state.
FIG. 2
is a timing chart showing an operation before/after the conventional single chip microcomputer is changed from a high-speed operation to a low-speed operation. In the conventional single chip microcomputer constructed in the foregoing manner, when an operating speed is changed from high-speed operation to low-speed operation, the CPU
110
transmits a high-level switching signal A
1
to the control circuit
112
based on a program stored in the ROM
107
. Then, upon having received the high-level switching signal A
1
, the control circuit
112
sets the level of an oscillator control signal G
1
to be low by a specified timing. Accordingly, the operation of the first oscillator
103
is stopped. On the other hand, the level of an oscillator control signal C
2
is always high, and the second oscillator
104
is in a constantly operated state. Thus, it is only the second oscillator
104
that is operated during a low-speed operation.
Therefore, in the conventional single chip microcomputer, since power consumed by the first oscillator
103
during the low-speed operation is 0, a charging/discharging current is reduced, bringing about a reduction in power consumption like that shown in FIG.
2
.
However, there is a drawback inherent in such a conventional single chip microcomputer. Specifically, even if the charging/discharging current is reduced, no reduction occurs in an OFF leakage current caused to flow when a transistor in the chip is microstructured in dimension. Consequently, in a microstructuring process applied to the microcomputer requiring a high-speed operation, a leakage current component is increased, which makes it impossible to achieve low power consumption. If a requested operating speed is not so high, the OFF leakage current can be suppressed by setting high a threshold voltage Vt of the transistor, even when the transistor is microstructured. If a high-speed operation is requested, however, since a low threshold voltage Vt is necessary, power consumption during the low-speed operation is increased by the OFF leakage current when the transistor is microstructured.
Under these circumstances, regarding the microcomputer requiring the high-speed operation, one capable of reducing power consumption has been proposed (Japanese Patent Laid-open Application No. Sho. 60-10318). In the microcomputer described therein, two kinds of power supply voltages and clock signals are switched according to an operating speed, and power consumption is thereby reduced during the low-speed operation. The power supply voltages and the clock signals are simultaneously switched by a control circuit.
However, even in the conventional microcomputer described in Japanese Patent Laid-Open Application No. Sho. 60-10318, power consumption during the low-speed operation is still large, and there is a demand for a further reduction in power consumption.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a single chip microcomputer capable of reducing power consumption.
According to one aspect of the present invention, a single chip microcomputer comprises a central processing unit which stores a program executed by the central processing unit, a read only memory, a random access memory which holds data processed by the central processing unit, an oscillator which supplies a clock signal to the central processing unit, a peripheral circuit which transfers a signal to the central processing unit and receives a signal from the central processing unit, and a control circuit. The control circuit supplies a first voltage to the central processing unit, the read only memory, the random access memory and the peripheral circuit in synchronization with rising/falling of the clock signal. The control circuit supplies a second voltage to the central processing unit with passage of predetermined time after the rising/falling of the clock signal. The first voltage enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to change their operations. The second voltage is lower than the first voltage, and enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to maintain their operations.
According to the aspect of the present invention, a voltage supplied to each of the central processing unit, the read only memory, the random access memory and the peripheral circuit is set equal to one for enabling the respective units and circuits to be operated in synchronization with rising/falling of the clock signal. In other words, a voltage is set for enabling the respective units and circuits to change their operations. In addition, with passage of predetermined time after the rising/falling of the Clock signal, a voltage is reduced to one for enabling the respective units and circuits to maintain their operations. Accordingly, leakage current is reduced while the stable operat
Choate Hall & Stewart
Lee Thomas
NEC Electronics Corporation
Yanchus, III Paul
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