Single chip integrated circuit with external bus interface

Details Single chip integrated circuit with external bus interface Single chip integrated circuit with external bus interface

1997-04-08

2001-05-01

Sheikh, Ayaz (Department: 2155)

Electrical computers and digital processing systems: support

Computer power control

C713S322000, C713S323000, C713S340000, C713S400000, C714S037000, C714S038110, C714S042000, C714S726000, C714S733000, C714S736000, C714S738000, C714S739000, C714S742000, C714S745000, C365S203000, C365S226000, C712S001000, C712S039000, C712S040000

Reexamination Certificate

active

06226753

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (data processor) having a memory and a microprocessor built therein, and more particularly to a semiconductor integrated circuit which suppresses power consumption.
2. Description of the Background Art
Recently, semiconductor integrated circuits have rapidly become finer. At present, a memory and a microprocessor can be built in one chip. In the past when a memory and a microprocessor could not be built in one chip, the memory chip and the microprocessor chip were interconnected by wiring. In the two chip system, it was sufficient that a signal sent to the wiring was observed in order to observe a signal sent between the memory and the microprocessor. In addition, the signal sent between the memory and the microprocessor could always be observed. However, since the memory and the microprocessor are now built on a single chip, there is a problem that the signal sent between the memory and the microprocessor (hereinafter referred to as an “internal signal”) can only be observed with difficulty.
In order to more easily observe the internal signal, a semiconductor integrated circuit shown in
FIG. 9
has been developed.
FIG. 9
is a block diagram showing an example of a semiconductor integrated circuit
200
having a memory and a microprocessor built in one chip according to the prior art.
The internal signal includes address information, data inputted to or outputted from the memory, and a DRAM access control signal. The DRAM access control signal includes a bus status signal, a byte control signal, and a read/write signal.
P
1
denotes an external terminal for outputting the bus status signal. P
2
denotes an external terminal for inputting and outputting the byte control signal. P
3
denotes an external terminal for inputting and outputting the read/write signal. P
4
denotes an external terminal for inputting and outputting the address information. P
5
denotes an external terminal for inputting and outputting data. S
6
denotes a signal line (an address bus) for mutually connecting a microprocessor
1
through a DRAM
2
, a cache memory
3
and a memory controller
4
to send the address information. S
7
denotes a signal line (data bus) for connecting the microprocessor
1
, the DRAM
2
and the cache memory
3
to send the data.
An external bus interface
51
controls the outputs of the address information, the data and the DRAM access control signal described above. S
1
to S
5
denote signal lines for connecting the external bus interface
51
to the external terminals P
1
to P
5
, respectively.
The features of the operation of the semiconductor integrated circuit
200
are as follows. The internal signal is always outputted to the external terminals P
1
to P
5
. Accordingly, the internal signal can be easily observed by observing the signals in the external terminals P
1
to P
5
. In other words, a signal sent between the memory and the microprocessor can always be observed in the same manner as in a chip in which the memory and the microprocessor were not provided on a common chip.
The microprocessor
1
of the semiconductor integrated circuit
200
can also gain access to external memories. A signal exchange necessary for this access is performed by using the external terminals P
1
to P
5
.
FIG. 10
is a general diagram in which the semiconductor integrated circuit
200
is connected to a DRAM
300
that is an external memory. The external terminals P
1
to P
5
are connected to external terminals Q
1
to Q
5
of the DRAM
300
, respectively (whose functions correspond to those of the external terminals P
1
to P
5
, respectively).
Although it is necessary to output an internal signal from each of the external terminals P
1
to P
5
in order to monitor the internal operation when testing the semiconductor integrated circuit
200
, it is not necessary to output the internal signal when an ordinary user makes use of the semiconductor integrated circuit
200
. According to the prior art, however, the internal signal is outputted from each of the external terminals P
1
to P
5
even when it is unnecessary. In general, power is consumed when the value of the outputted signal is changed. With the semiconductor integrated circuit
200
, accordingly, the internal signal is outputted in spite of this being an unnecessary operation. Consequently, unnecessary power consumption is the result of this output.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems of the prior art, it is an object of the present invention to provide a semiconductor integrated circuit for controlling outputs to suppress power consumption.
A first aspect of the present invention is directed to a semiconductor integrated circuit, comprising a data processing section for processing data, a memory for storing the data, external terminals, and an output control section for giving, to the external terminals respectively, an internal signal used for the processing in a first state and a stationary value in a second state which is different from the first state.
A second aspect of the present invention is directed to the semiconductor integrated circuit, wherein the output control section receives the internal signal and an output control signal which indicates either the first state should be output or the second state, and internal operation of the semiconductor integrated circuit is monitored in the first state and the internal operation of the semiconductor integrated circuit does not need to be monitored in the second state.
A third aspect of the present invention is directed to the semiconductor integrated circuit, further comprising an external input terminal for inputting a output control signal from a circuit other than the semiconductor integrated circuit.
A fourth aspect of the present invention is directed to the semiconductor integrated circuit, further comprising an output control signal storing section for outputting a stored value as the output control signal, wherein a program to be executed by the data processing section to write the value to the output control signal storing section is stored in the memory.
A fifth aspect of the present invention is directed to the semiconductor integrated circuit, further comprising an input terminal for inputting, from a circuit other than the present semiconductor integrated circuit, an enabling signal to enable writing of a value to the output control signal storing section, wherein the data processing section can write a value to the output control signal storing section only in the case where the enabling signal is given from the external input terminal.
A sixth aspect of the present invention is directed to the semiconductor integrated circuit further comprising an output control signal generating section which includes a fuse and outputs which supplies to the output control section, the output control signal indicative of the second or first state corresponding to whether the fuse is disconnected or not.
According to the first aspect of the present invention, the case where the internal signal is given to the external terminals is restricted to only the first state. Consequently, it is possible to obtain an effect that power consumption can be suppressed.
According to the second aspect of the present invention, the output control signal is used, which indicates the second state where the internal signal is processed only on its inside or not at all. Consequently, the output control section can be implemented by a simple circuit for inputting the output control signal and the internal signal.
According to the third aspect of the present invention, the external input terminal for inputting the output control signal from outside the circuit is provided. Consequently, it is possible to control that the internal signal of the semiconductor integrated circuit is monitored on the outside or not.
According to the fourth aspect of the present invention, the outputs of the external terminals are controlled by the pro

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