Skipping clock interrupts during system inactivity to reduce pow

Details Skipping clock interrupts during system inactivity to reduce pow Skipping clock interrupts during system inactivity to reduce pow

1999-01-14

2000-12-12

Auve, Glenn A.

Electrical computers and digital processing systems: support

Computer power control

Power conservation

713320, 713324, 326 98, G06F 126, G06F 128, G06F 130

Patent

active

061611875

ABSTRACT:
A method for reducing power consumption in a computer system is provided wherein the computer system includes a system bus interface connected by a signal line to a power supply and/or clock circuitry for the central processing unit, each having the capability to change the characteristic of its output responsive to the signal line for placing the central processing unit in a low-power consuming state. The system bus interface chip further including a storage location and counter for storing the type and quantity of interrupt assertions during the period of time when the central processing unit is in the low power consuming state.
The system software determines the desired period of time to put the central processing unit into the low-power consuming safe and does not return it to normal power consuming state until the time period has expired, a non interval clock interrupt is asserted, or another critical event occurs that needs immediate CPU attention.
When one of these conditions arises, the signal line changes polarity, the power supply and/or clock circuitry returns normal operating levels to the CPU, and the system bus interface presents all interrupts that asserted while the CPU was in the low-power consuming state to the CPU so it can continue normal operation.

REFERENCES:
patent: 5222076 (1993-06-01), Ng et al.
patent: 5335540 (1994-08-01), Bowler et al.
patent: 5530879 (1996-06-01), Crump et al.

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