Input/output system with mask register bit control of memory...

Instruction causing swap of base address from segment...

Instruction set for bi-directional conversion and transfer...

Instruction-parallel processor with...

Instructions for ordering execution in pipelined processes

Instructions for ordering execution in pipelined processes

Instructions for ordering execution in pipelined processes

Inter-CPU data transfer device

Limiting entries searched in load reorder queue to between...

Load store unit with replay mechanism

Load/move and duplicate instructions for a processor

Load/move duplicate instructions for a processor

Magnetic disc control apparatus with parallel data transfer...

Managing stack transfers in a register-based processor

Managing stack transfers in a register-based processor

Mechanism for avoiding check stops in speculative accesses...

Mechanism for fast access to control space in a pipeline...

Mechanism for irrevocable transactions

Memory access address comparison of load and store queques

Memory access consolidation for SIMD processing elements...