Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
2001-10-30
2003-06-10
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C712S040000, C712S212000, C360S048000, C714S772000, C714S798000, C714S784000
Reexamination Certificate
active
06578136
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a magnetic disc apparatus for use in information processing apparatus such as a computer, and more particularly, to a magnetic disc apparatus including an LSI for magnetic disc apparatus which is capable of performing high speed read and write operations by parallelly reading and writing data from and into the magnetic disc apparatus, as well as effectively utilizing recording surfaces of magnetic discs by selecting a spare track or a spare sector in place of a defective track or a defective sector on the magnetic disc.
There has been a conventional magnetic disc apparatus known as a parallel read and write type, as described in Japanese Patent Application Laid-open Publication No. 61-145767, which divides data belonging to a single sector on a data recording surface to simultaneously record the divided data in parallel, and simultaneously reads data recorded on respective data recording surfaces in parallel and synthesizes the same to data in sector units to thereby increase a data transfer speed.
As a counterpart of the above-mentioned parallel read and write type magnetic disc apparatus, there is a serial read and write type magnetic disc apparatus whose internal structure is shown in a block diagram of FIG.
17
.
In
FIG. 17
, reference numeral
1
designates a host computer,
2
a magnetic disc apparatus,
3
a host interface control unit,
4
a buffer memory,
5
a disc control unit,
6
a microprocessor,
8
a recording and reproducing unit,
9
an encoder/decoder circuit,
11
a head circuit,
14
a parallel interface.
When a parallel data of, for example, eight bits is supplied from the host computer
1
through the parallel interface
14
, the parallel data is delivered in the magnetic disc apparatus
2
from the host interface control unit
3
to the disc control unit
5
where the parallel data is parallel-to-serial converted. The serially converted data is written one bit by one bit on a recording surface of a magnetic disc, not shown, through the encoder/decoder circuit
9
by the head circuit
11
as serial data. On the other hand, data serially read one bit by one bit is delivered through the encoder/decoder circuit
9
to the disc control unit
5
. The disc control unit
5
converts the serial data to a parallel form, and this parallel data is transferred to the host computer
1
through the host interface control unit
3
and the parallel interface
14
.
FIG. 8
is a block diagram showing the disc control unit
5
as shown in
FIG. 17
in detail.
In
FIG. 18
, reference numeral
24
designates a MPU (microprocessor unit) interface unit,
25
a host interface control unit,
7
a serial/parallel conversion unit,
27
a drive control unit, and
28
an ECC unit for detecting and correcting data errors. It will be appreciated that a serial data transmission path is established by data transmission paths from the serial/parallel conversion unit
7
to the drive control unit
27
and the ECC unit, and from the drive control unit
27
to the encoder/decoder unit
9
and thereafter.
FIG. 19
is a block diagram showing an internal structure of a conventional parallel read and write type magnetic disc apparatus. A magnetic disc apparatus
2
shown in this drawing comprises a plurality of disc-shaped recording surfaces constituting a single cylinder and read and write heads respectively corresponding to the respective recording surfaces, as shown in FIG.
20
. When a disc control unit
5
receives m-bit parallel data from a host computer
1
, the parallel data is divided into two data train respectively comprising (m/2)-bit parallel data which are separately parallel-to-serial converted by a serial/parallel conversion unit
7
. The two serial bit train outputted as the results are encoded by the encoder/decoder circuit
9
, and then they are assigned to two heads selected from a plurality of heads (by a head circuit
11
). These two data train is parallelly written on two disc-shaped recording surfaces corresponding to the selected two heads. On the other hand, when data is read from recording surfaces, two data trains are parallelly read from two disc-shaped recording surfaces corresponding to two heads. The read data sequences are decoded, serial-to-parallel converted, and then integrated to a m-bit parallel data by the disc control unit
5
and outputted to the host computer
1
.
FIG. 20
is a lateral view showing a structure of a magnetic disc apparatus.
In this drawing, five recording discs
51
are concentrically supported to constitute a cylinder, wherein the upper surface and the lower surface of each disc respectively constitute recording surfaces. Specifically, the upper surface and the lower surface of the respective five recording discs
51
are utilized as recording surfaces, so that there are totally ten recording surfaces which correspond to a servo surface
52
and first to ninth data recording surfaces
53
-
1
to
53
-
9
. Also, ten heads H are provided for the respective recording surfaces so as to be associated with one another.
FIG. 21
is a block daigram showing a circuit arrangement of the recording and reproducing unit
8
of the conventional magnetic disc apparatus shown in
FIG. 19
in a data write operation.
In
FIG. 21
, the encoder/decoder unit
9
is shown as comprising n encoder circuits
16
while the head circuit
11
n head amplifiers
17
and n heads
18
upon writing data. If 2-bit parallel data is to be written, n is naturally
2
. Reference numeral
15
designates a write clock generation circuit,
19
an NRZ (Non-Return to Zero) signal.
FIG. 22
is a block daigram showing a circuit arrangement of the recording and reproducing unit
8
of the conventional disc apparatus shown in
FIG. 19
when data is read.
In
FIG. 22
, the encoder/decoder unit
9
is shown as comprising n decoder circuits
22
and n waveform shaper circuits
23
, and the head circuit
11
n head amplifiers
17
and n head
18
, upon reading data. However, as mentioned above, if 2-bit parallel data is to be read, n is naturally 2. Reference numeral
21
designates a phase synchronization circuit.
The above-mentioned prior art is useful in achieving a high speed data transfer by performing parallel write and read operations, however, it does not consider a combination of data recording surfaces on which data divided from parallel data are to be stored, which results in always providing fixed combinations of the recording surfaces for a simultaneous read or write operation. For this reason, the prior art implies problems in a decrease of a storage capacity due to defective recording surfaces, which is remarkably important in a parallel read and write operation, and a deterioration in a data transfer speed caused by reassignment of spare tracks and spare sectors in place of defective tracks and defective sectors.
For example, as shown in the previously explained
FIG. 20
, in the magnetic disc apparatus of a dedicated servo system or a servo system using a servo surface employing five discs
51
, assuming that a two-bit parallel recording is performed where parallel data transferred from the host computer
1
is divided into two data trains, and a write or read operation of the two data trains is simultaneously carried out by the use of two data recording surfaces.
As shown in
FIG. 20
, nine out of ten recording surfaces are used as data recording surfaces (data recording surfaces
53
-
1
to
53
-
9
). Therefore, if two surfaces are fixedly combined to be one unit for the two-bit parallel recording, one data recording surface inevitably remains unused and cannot be utilized for reading and writing data.
If the recording surfaces for the two-bit parallel recording are made by combinations of the data recording surfaces
53
-
1
and
53
-
2
,
53
-
3
and
53
-
4
,
53
-
5
and
53
-
6
, and
53
-
7
and
53
-
8
, the data recording surface
53
-
9
cannot be used for writing and reading data and remains unused.
On the above-mentioned occasion, assuming that a track on the data recording surface
53
-
6
on
Hirose Tsuneo
Karasawa Noriyuki
Kawamura Satoshi
Kubo Mitsuru
Oeda Takashi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Pan Daniel H.
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