Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
2007-01-16
2007-01-16
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
Reexamination Certificate
active
10458457
ABSTRACT:
A microprocessor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.
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Filippo Michael A.
Gopal Rama S.
Pickett James K.
Sander Benjamin T.
Advanced Micro Devices , Inc.
Coleman Eric
Kowert Robert C.
Meyertons, Hood, Kivlin, Kowert & Goetzel P.c.
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