Mechanism for avoiding check stops in speculative accesses...

Details Mechanism for avoiding check stops in speculative accesses... Mechanism for avoiding check stops in speculative accesses...

2011-05-24

2011-05-24

Lee, Chun-Kuan (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

C712S220000

Reexamination Certificate

active

07949859

ABSTRACT:
A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.

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