Paired register exchange using renaming register map
Pairing of load-ALU-store with conditional branch
Partitioned multiply and add/subtract instruction for CPU with i
Performance enhancement for code transitions of floating...
Pipelined processor including a loosely coupled side pipe
Pipelined, superscalar floating point unit having...
Pipelined, superscalar floating point unit having...
Piping rounding mode bits with floating point instructions...
Power reduction mechanism for floating point register file...
Processing for associated data size saturation flag history...
Processing unit incorporating instruction-based persistent...
Processing unit incorporating special purpose register for...
Processing unit with cross-coupled ALUs/accumulators and...
Processor apparatus and method of processing multiple data...
Processor architecture having two or more floating-point...
Processor having efficient function estimate instructions
Processor having efficient function estimate instructions
Processor that predicts floating point instruction latency...
Processor which can favorably execute a rounding process compose
Processor which can favorably execute a rounding process...