Processor which can favorably execute a rounding process compose

Details Processor which can favorably execute a rounding process compose Processor which can favorably execute a rounding process compose

1997-12-01

1999-10-26

Ellis, Richard L.

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

708551, 708552, G06F 9302, G06F 738

Patent

active

059745401

ABSTRACT:
A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction "MCSST D1" is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer "0x0000.sub.-- 00FF". The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is "ON". The multiplexer 24 outputs one of the maximum value "0x0000.sub.-- 00FF" generated by the constant generator 21, the zero value "0x0000.sub.-- 0000" generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

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