Pipelined processor including a loosely coupled side pipe

Details Pipelined processor including a loosely coupled side pipe Pipelined processor including a loosely coupled side pipe

2005-07-12

2005-07-12

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C712S223000

Reexamination Certificate

active

06918028

ABSTRACT:
A digital data processor having a main pipeline to which a side pipe is loosely coupled. In particular, the side pipe is coupled to the main pipeline at a point after which an instruction entering the side pipe cannot cause an exception. When such an instruction enters the first stage of the side pipe, a copy or “ghost” of this instruction is created. While the actual instruction flows down the side pipe, this ghost instruction is allowed to flow independently down the main pipeline as if it were a non-squashable no-op. When the ghost reaches the retirement stage of the main pipeline, it is retired in normal program order, regardless of the status of the actual instruction. However, in addition, each system resource that is still waiting for a result from the actual instruction is marked appropriately. When the actual instruction finally completes in the side pipe, the only consequence, other than those local to the side pipe itself, is that any results are forwarded to the awaiting resources. If it should happen that a resource has been reallocated to a more recent instruction while the actual instruction is still in flight, the forwarded result is discarded upon arrival; otherwise, the resource is updated using the forwarded result. As a result of employing such a pipe coupling mechanism, the number of pipe stages that must be traversed by instructions other than those requiring a side pipe resource may be reduced. One disclosed example of such a side pipe is a multiply accumulate unit suitable for use in digital signal processing applications, whereby the performance of control type instructions is greatly improved.

REFERENCES:
patent: 5442769 (1995-08-01), Corcoran et al.
patent: 5463745 (1995-10-01), Vidwans et al.
patent: 5490255 (1996-02-01), Rawlinson et al.
patent: 5559975 (1996-09-01), Christie et al.
patent: 5574871 (1996-11-01), Hoyt et al.
patent: 5838939 (1998-11-01), Sutherland
patent: 5931934 (1999-08-01), Li et al.
patent: 5948098 (1999-09-01), Leung et al.
patent: 5996059 (1999-11-01), Porten et al.
patent: 6085315 (2000-07-01), Fleck et al.
patent: 6345351 (2002-02-01), Holmberg
patent: 6438681 (2002-08-01), Arnold et al.
Rosenberg, Jerry M. Dictionary of Computers, Information, Processing, & Telecommunications. Second Edition. New York; John Wiley & Sons, Inc. ©1987. pp. 353 and 649.
MMX technology developer's guide. “Chapter 2: Overview of Processor Architecture and Pipelines”. Intel Corporation. ©1997.

Affiliated with

Also associated with

Rating

Pipelined processor including a loosely coupled side pipe does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipelined processor including a loosely coupled side pipe, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined processor including a loosely coupled side pipe will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3370454