Processor that predicts floating point instruction latency...

Details Processor that predicts floating point instruction latency... Processor that predicts floating point instruction latency...

2007-10-16

2007-10-16

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C712S221000

Reexamination Certificate

active

10700391

ABSTRACT:
A processor includes a prediction circuit and a floating point unit. The prediction circuit is configured to predict an execution latency of a floating point operation. The floating point unit is coupled to receive the floating point operation for execution, and is configured to detect a misprediction of the execution latency. In some embodiments, an exception may be taken in response to the misprediction. In other embodiments, the floating point operation may be rescheduled with the corrected execution latency.

REFERENCES:
patent: 5631859 (1997-05-01), Markstein et al.
patent: 5802386 (1998-09-01), Kahle et al.
patent: 5842036 (1998-11-01), Hinton et al.
patent: 6029243 (2000-02-01), Pontius et al.
patent: 6542984 (2003-04-01), Keller et al.
patent: 2003/0061467 (2003-03-01), Yeh et al.
patent: 2003/0126406 (2003-07-01), Hammarlund et al.
Trace Cache by Rotenberg, Bennett and Smith.

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