Processing for associated data size saturation flag history...

Details Processing for associated data size saturation flag history... Processing for associated data size saturation flag history...

2007-04-30

2008-05-13

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C712S022000, C712S034000

Reexamination Certificate

active

07373488

ABSTRACT:
A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a saturating operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated. A second coprocessor instruction has a second format identifying a saturation history processing operation and a saturation data size. An operand for the processing operation is determined based on the saturation data size, and the processing operation is executed on the saturation flags and the operand for the saturation data size. Condition code flags are stored in a status register to indicate the result of processing operation.

REFERENCES:
patent: 4750110 (1988-06-01), Mothersole et al.
patent: 4873630 (1989-10-01), Rusterholz et al.
patent: 4894768 (1990-01-01), Iwasaki et al.
patent: 5073864 (1991-12-01), Methvin et al.
patent: 5125095 (1992-06-01), Nakazawa et al.
patent: 5420809 (1995-05-01), Read et al.
patent: 5420989 (1995-05-01), Maher et al.
patent: 5696985 (1997-12-01), Crump et al.
patent: 5721892 (1998-02-01), Peleg et al.
patent: 5734874 (1998-03-01), Van Hook et al.
patent: 5802336 (1998-09-01), Peleg et al.
patent: 5805875 (1998-09-01), Asanovic
patent: 5815715 (1998-09-01), Ku.cedilla.uk.cedilla.akar
patent: 5822619 (1998-10-01), Sidwell
patent: 5838984 (1998-11-01), Nguyen et al.
patent: 5893066 (1999-04-01), Hong
patent: 5915109 (1999-06-01), Nakakimura et al.
patent: 5923893 (1999-07-01), Moyer et al.
patent: 5930519 (1999-07-01), Krech, Jr.
patent: 5933650 (1999-08-01), van Hook et al.
patent: 5936872 (1999-08-01), Fischer et al.
patent: 5996057 (1999-11-01), Scales et al.
patent: 6006315 (1999-12-01), Park
patent: 6247113 (2001-06-01), Jaggar
patent: 6282633 (2001-08-01), Killian et al.
patent: 6298438 (2001-10-01), Thayer et al.
patent: 6332186 (2001-12-01), Elwood et al.
patent: 6430684 (2002-08-01), Bosshart
patent: 6502117 (2002-12-01), Golliver et al.
patent: 6530012 (2003-03-01), Wilson
patent: 6546480 (2003-04-01), Mandavilli et al.
patent: 6550000 (2003-04-01), Minematsu et al.
patent: 6671797 (2003-12-01), Golston
patent: 6748521 (2004-06-01), Hoyle
patent: 6754804 (2004-06-01), Hudepohl et al.
patent: 6757820 (2004-06-01), Sudharsanan et al.
patent: 6829697 (2004-12-01), Davis et al.
patent: 6865663 (2005-03-01), Barry
patent: 2002/0065860 (2002-05-01), Grisenthwaite et al.
patent: 2002/0083311 (2002-06-01), Paver
patent: 2003/0120903 (2003-06-01), Roussel
patent: 2003/0167460 (2003-09-01), Desai et al.
patent: 2003/0204819 (2003-10-01), Matsumoto et al.
patent: 2004/0073773 (2004-04-01), Demjanenko
patent: WO 97/08608 (1997-03-01), None
patent: WO 00/43868 (2000-07-01), None
U.S. Appl. No. 10/263,246, filed Oct. 2002, Paver et al.
AMD Inc., AMD Extensions to the 3Dnow!(tm) and MMX(tm) Instructions Sets Manual , Mar. 2000, 22466D/0, AMD Inc., Santa Clara, CA USA.
ARM Ltd., ARM Instuction Set Quick Reference Card, Oct. 1999; Arm QRC 0001D, ARM Ltd., Cambridge, UK.
Brash, D., The ARM Architecture Version 6 (ARMv6), Jan. 2002, ARM White Paper, ARM Ltd., Cambridge UK.
Lewis, A., MPEG-4 Over Wireless Networks, 2000, ARM White Paper, ARM Ltd., Cambridge UK.
Wragg, B & Carpenter, P., An Optimised Software Solution for an ARM Powered(tm) MP# Decoder, Oct. 2000, ARM White Paper, ARM Ltd., Cambridge UK.
R.B. Grant et al.,The Scalable Processor Architecture(SPARC), Intellectual Leverage, San Francisco, Feb. 29-Mar. 4, 1988, Computer Society International Conference Washington, IEEE Comp. Soc. Press, US, vol. Conf. 33, Feb. 29, 1988, pp. 278-283.
Derby, J. et al. “A High-Performance Embedded DSP Core with Novel SIMD Features.” ICASSP, IEEE 0-7803-3, 2003.
Lerner, Boris. “Parallel Implementation of Fixed-Point FFT's on TigerSHARC® Processors, Analog Devices,” EE-263, rev 1, Feb. 3, 2005.
Ikei, Mitsuru. “Basic of IA-64 Processor.” Published from Ohmsha Corporation on Aug. 25, 2000., pp. 150, 160 and 161.

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