Partitioned multiply and add/subtract instruction for CPU with i

Details Partitioned multiply and add/subtract instruction for CPU with i Partitioned multiply and add/subtract instruction for CPU with i

1996-10-10

1999-11-30

Kim, Kenneth S.

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

708501, 708523, 712 5, 712 9, 712 22, G06F 1716

Patent

active

059960663

ABSTRACT:
An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executing them are disclosed to optimize the execution of graphics instruction with minimal additional hardware for a general purpose CPU.

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