Digital signal processor with wait state register

Distributed extensible processing architecture for digital signa

DPGA-coupled microprocessors

DSP coprocessor having control flags mapped to a dual port...

DSP with dual-mac processor and dual-mac coprocessor

DSP with wait state registers having at least two portions

Dual instruction set architecture

Dual ROM microprogrammable microcontroller and universal...

Dual-mode VLIW architecture providing a software-controlled...

Dynamic pipelines with reusable logic elements controlled by...

Dynamic resource allocation among master processors that...

Dynamic scheduling mechanism for an asynchronous/isochronous...

Dynamically reconfigurable computing using a processing unit...