Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1998-08-21
2002-01-01
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S006000, C712S007000, C709S232000, C709S233000, C709S236000, C709S238000
Reexamination Certificate
active
06336179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to computer systems and more particularly to efficiently scheduling transfers on a computer system bus having a relatively high bandwidth and a relatively low pin count.
2. Description of the Related Art
In current and future personal computer systems, two basic types of data are transferred between integrated circuits: isochronous data and asynchronous data. Isochronous data refers to data used in real-time data streams such as audio data or motion-picture video data. Asynchronous data is used for all other transfers, such as central processing unit (CPU) accesses to peripherals or bulk data transmissions from a hard drive into system memory.
At present, buses in computer systems provide inadequate support for transfer of both isochronous and asynchronous data on the same bus. For example, the peripheral component interface (PCI) bus, a major input/output bus in present personal computer architectures, does not support isochronous data. If a computer system gives asynchronous data priority or treats isochronous data as asynchronous data, then those functions relying on real time data, such as motion-picture video, may not function satisfactorily. Alternatively, if a computer system prioritizes isochronous data, then the performance of the computer system can suffer since the latency of asynchronous data can become unacceptably long. As computer systems are called on to perform more and more real time activity, such as real time video, it becomes more critical that asynchronous and isochronous data be treated in a manner that prevents problems from occurring in the real time tasks without adversely effecting other aspects of computer performance. Thus, there exists a need to appropriately accommodate both kinds of data in present and future computer systems without adversely affecting system performance.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a method and apparatus to dynamically schedule isochronous transfers on an interconnect bus. In accordance with one aspect of the invention, an apparatus determines priority of data transfer over a bus transferring asynchronous and isochronous data. The apparatus includes a plurality of sources that provide transfer count values indicative of an amount of isochronous data to transfer over the bus during a specific time period from the respective sources. A selector circuit is coupled to the sources and selectably provides one of the count values to a down counter. The down counter sequentially loads count values from the sources requesting transfer of isochronous data during the time period. The apparatus further includes an up/down counter and a control circuit coupled to the down counter and the up/down counter and the selector circuit. The control circuit configures the up/down counter to count up while the down counter is counting, thereby providing a remaining count value indicative of a remaining amount of isochronous data requested to be transferred during the time period from the plurality of sources requesting transfer of isochronous data.
In accordance with another aspect of the invention, a method for determining an amount of data to transfer over a bus from a plurality of sources during a time period, includes sequentially providing a plurality of numbers to a first counter from respective ones of the sources requesting transfer of data. Each of the numbers represents an amount of data to transfer over the bus from the respective sources. The first counter sequentially counts the plurality of numbers. A count value in a second counter is selectably incremented when the first counter is counting, to provide a remaining count value indicative of a remaining amount of data to transfer in the time period from the plurality of sources requesting transfer of data during the time period. The plurality of sources provide isochronous data and the method further includes decrementing the remaining count value in the second counter for each isochronous transfer on the bus after the remaining amount of data to transfer has been determined from all sources requesting transfer. The method also includes tracking the time remaining in the time period in a third counter and comparing the remaining count value to the time remaining in the time period to determine a priority mode on the bus. The bus switches to isochronous priority mode according to a comparison of the remaining count value and the time remaining in the time period.
REFERENCES:
patent: 5329531 (1994-07-01), Diepstraten et al.
patent: 5422883 (1995-06-01), Hauris et al.
patent: 5450411 (1995-09-01), Heil
patent: 5487170 (1996-01-01), Bass et al.
patent: 5570201 (1996-10-01), Yokota
patent: 5604742 (1997-02-01), Colmant et al.
patent: 5621898 (1997-04-01), Wooten
patent: 5640392 (1997-06-01), Hayashi
patent: 5742847 (1998-04-01), Knoll et al.
patent: 5758105 (1998-05-01), Kelley et al.
patent: 5761430 (1998-06-01), Gross et al.
patent: 5761431 (1998-06-01), Gross et al.
patent: 5761448 (1998-06-01), Adamson et al.
patent: 5845152 (1998-12-01), Anderson et al.
patent: 5872998 (1999-02-01), Chee
patent: 5948080 (1999-09-01), Baker
patent: 5991304 (1999-11-01), Abramson
patent: 6032211 (2000-02-01), Hewitt
patent: 6061411 (2000-05-01), Wooten
Advanced Micro Devices , Inc.
Nguyen Dzung C.
Pan Daniel H.
Zagorin O'Brien & Graham LLP
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