Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1999-01-27
2001-12-25
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S035000, C712S031000, C712S220000
Reexamination Certificate
active
06334179
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to DSP systems, and more particularly to the manner in which DSP coprocessors are utilised.
DSP coprocessors allow performance of a number of different operations within a single clock cycle. These operations typically include multiplication and accumulation, one or more data memory reads or writes, and incrementing address pointer registers. Typical applications are control of AC or DC motors, speech processing, vehicle engine knock detection, modems, frequency analysis circuits, and data communication equipment generally.
While DSPs are very efficient for the specific tasks involved, they generally suffer from the problem of requiring a large degree of hand-optimised assembly language to achieve desired performance. This has arisen from the complex nature of such processors.
OBJECTS OF THE INVENTION
One object is to provide a DSP coprocessor which operates efficiently, and which may also be controlled in a flexible manner
Another object is to minimise size and cost of a DSP system.
SUMMARY OF THE INVENTION
According to the invention, there is provided a DSP coprocessor comprising:
an arithmetic logic unit;
an address generation unit;
a program control unit;
means for addressing memory to retrieve instructions for a function selected from a library of functions; and
activation means for receiving an external input macro command to activate a selected function.
The addressing and activation means allow the coprocessor to operate independently after an external circuit or interface has activated a selected function. This provides excellent design and control flexibility.
In one embodiment, the memory storing the library of functions is a non-volatile memory.
In another embodiment, the program control unit comprises the means for addressing the memory storing the library of functions.
In one embodiment, the program control unit comprises the activation means.
In another embodiment, the activation means comprises means for addressing an external memory to retrieve the macro command.
In another embodiment, the external memory comprises a shared random access memory which is accessable by a host processor.
Preferably, the shared random access memory is mapped with a parameters section, and the coprocessor comprises means for reading initialisation instructions from the parameters section.
In one embodiment, the shared access memory is mapped with a parameters section, and the coprocessor comprises means for reading locations for data and results from the parameters section.
In a further embodiment, the non-volatile memory instructions are in very long instruction word (VLIW) format.
In one embodiment, the program control unit comprises means for addressing programmable instructions in the shared random access memory. In the latter embodiment, the shared random access memory preferably has a partitioned section for instructions.
In one embodiment, the program control unit comprises means for addressing programmable instructions in the shared random access memory and means for decoding the instructions.
In another embodiment, program control unit PC values are within pre-determined ranges and the program control unit comprises means for determining the source of the next instruction according to the value of the PC. In the latter embodiment, the coprocessor preferably comprises means for determining the source of a next instruction, and missing a fetch operation in the current cycle if the source of the next instruction is from the programmable instruction section and the current instruction accesses the shared random access memory.
In a further embodiment, the shared random access memory includes a dual port section and busy and bus request flags are mapped to said section, whereby a host may read or write a flag without affecting coprocessor operation.
According to another aspect the invention provides a DSP coprocessor system comprising a DSP coprocessor as described above and a shared random access memory comprising means for allowing host processor access.
According to a further aspect, the invention provides a DSP coprocessor system as described above and further comprising a host processor.
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patent: 5784602 (1998-07-01), Glass et al.
patent: 0299075 (1989-01-01), None
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Patent Abstracts of Japan, vol. 6, No. 229, Nov. 16, 1982 and JP 57 130147 A (Tokyo Shibaura Denki KK), Aug. 12, 1982.
Costigan Paul
Curran Philip
Dunn Mark
Murray Brian
An Meng-Al T.
Jacobson & Holman PLLC
Lin Wen-Tai
Masaana Research Limited
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