System with wide operand architecture, and method

Systems for increasing register addressing space in...

Three operand instruction extension for X86 architecture

Trace unit

Trace unit with a decoder, a basic-block cache, a...

Trace unit with a trace builder

Unhandled operation handling in multiple instruction set...

Universal pointer implementation scheme for uniformly...

User initiated microcode modification

Using ECC/parity bits to store predecode information

Using IMPDEP2 for system commands related to Java...

Using IMPDEP2 for system commands related to Java...

Using multiple decoders and a reorder queue to decode...

Using on-chip and off-chip look-up tables indexed by...

Using padded instructions in a block-oriented cache

Variable address length compiler and processor improved in...

Variable reordering (Mux) instructions for parallel table...

Virtual memory system that is portable between different CPU...