Data processing system with bypass reorder buffer having...
Data processing system with partial bypass reorder buffer...
Data processor
Data processor
Data processor with individually writable register subword...
Decentralized exception processing system
Decode and execution synchronized pipeline processing using...
Deferring loads and stores when a load buffer or store...
Delay-slot control mechanism for microprocessors
Delayed deallocation of an arithmetic flags register
Dependence-chain processing using trace descriptors having...
Dependence-chain processing using trace descriptors having...
Dependency checking for reconfigurable logic
Dependency table for reducing dependency checking hardware
Dependency table for reducing dependency checking hardware
Design structure for single hot forward interconnect scheme...
Detecting raw hazards in an object-addressed memory...
Detection of data hazards between instructions by decoding...
Determining register availability for register renaming
Determining successful completion of an instruction by...