Deferring loads and stores when a load buffer or store...

Details Deferring loads and stores when a load buffer or store... Deferring loads and stores when a load buffer or store...

2007-11-06

2007-11-06

Kindred, Alford (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C712S237000

Reexamination Certificate

active

11106180

ABSTRACT:
One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store.

REFERENCES:
patent: 5630157 (1997-05-01), Dwyer, III
patent: 5802588 (1998-09-01), Ramagopal et al.
patent: 5881280 (1999-03-01), Gupta et al.

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