Retiring early-completion instructions to improve computer...
Scheduling instructions in a cascaded delayed execution...
Selective execution of deferred instructions in a processor...
Selectively deferring instructions issued in program order...
Speculative generation at address generation stage of...
Stall control
Stall-free pipelined cache for statically scheduled and...
Stick and spoke replay with selectable delays
Superscalar processing system and method for selectively...
Synchronising pipelines in a data processing apparatus
System, method and apparatus for allocating hardware...
Technique for ordering internal processor register accesses
Thread interleaving in a multithreaded embedded processor
Thread interleaving in a multithreaded embedded processor
Two pipeline stage microprocessor and method for processing...
Using a modified value GPR to enhance lookahead prefetch
Using a modified value GPR to enhance lookahead prefetch
Using a modified value GPR to enhance lookahead prefetch
Variable length instruction pipeline