Technique for ordering internal processor register accesses

Details Technique for ordering internal processor register accesses Technique for ordering internal processor register accesses

1998-02-02

2000-09-19

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reducing an impact of a stall or pipeline bubble

712231, 712244, 712206, G06F 938, G06F 9305

Patent

active

061227285

ABSTRACT:
A technique for processing register instructions in a pipeline data processor in which multiple instructions may be processed concurrently, and may therefore conflict with one another. Register instructions are identified with register groups indicating which processor registers are affected by the execution of the register instruction. The progress of the execution of the register instruction is then controlled depending upon the identified register groups, in order to avoid conflicts with other concurrently processed instructions.

REFERENCES:
patent: 5805849 (1998-09-01), Jordan et al.
patent: 5809325 (1998-09-01), Hinton et al.
Gieseke, Bruce A., et al. "A 600MHz Superscalar RISC Microprocessor With Out-of-Order Execution", ISSCC 97, Feb. 1997.
Gwennap, Linley, "Digital 21264 Sets New Standard Clock Speed, Complexity, Performance Surpass Records, But Still a Year Away", Microprocessor Report vol. 10, Issue 14: 1-11 Oct. 28, 1996.
Keller, Jim, "The 21264: A Superscalar Alpha Processor With Out-of-Order Execution", Microprocessor Forum, Oct. 1996.
Gieseke, Bruce A., et al. "FA 10.7: A 600Mhz Superscalar RISC Microprocessor with Out-Of-Order Execution", ISSCC 97: 176-177, 134-135, 394-395 (1997).

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