Using a modified value GPR to enhance lookahead prefetch

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

07620799

ABSTRACT:
Mechanisms to identify and speculatively execute future instructions during a stall condition are provided. In speculative mode, instruction operands may be invalid due to a number of reasons. Dependency and dirty bits are tracked and used to determine which speculative instructions are valid for execution. A modified value register storage and bit vector are used to improve the availability of speculative results that would otherwise be discarded once they leave the execution pipeline because they cannot be written to the architected registers. The modified general purpose registers are used to store speculative results when the corresponding instruction reaches writeback and the modified bit vector tracks the results that have been stored there. Younger speculative instructions that do not bypass directly from older instructions use this modified data when the corresponding bit in the modified bit vector indicates the data has been modified. Otherwise, data from the architected registers is used.

REFERENCES:
patent: 5471626 (1995-11-01), Carnevale et al.
patent: 5758051 (1998-05-01), Moreno et al.
patent: 5974538 (1999-10-01), Wilmot, II
patent: 5987594 (1999-11-01), Panwar et al.
patent: 6356918 (2002-03-01), Chuang et al.
patent: 6427207 (2002-07-01), Col et al.
patent: 6430683 (2002-08-01), Arimilli et al.
patent: 6473837 (2002-10-01), Hughes et al.
patent: 6950925 (2005-09-01), Sander et al.
patent: 7114060 (2006-09-01), Chaudhry et al.
patent: 7194604 (2007-03-01), Bigelow et al.
patent: 7257699 (2007-08-01), Chaudhry et al.
patent: 7376794 (2008-05-01), Steely, Jr. et al.
patent: 2003/0126406 (2003-07-01), Hammarlund et al.
patent: 2005/0055541 (2005-03-01), Aamodt et al.
patent: 2005/0223200 (2005-10-01), Tremblay et al.
patent: 2006/0149933 (2006-07-01), Eickemeyer et al.
patent: 2006/0149934 (2006-07-01), Eickemeyer et al.
patent: 2006/0149935 (2006-07-01), Eickemeyer et al.
patent: 2008/0077776 (2008-03-01), Eickemeyer et al.
Balasubramonian et al., “Dynamically Allocating Prcoessor Resources between Nearby and Distant ILP”, ACM Press, ACM Sigarch Computer Architecture News, May 2001, pp. 26-37.
Mutlu et al., “Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors”, IEEE Computer Society, Symposium on High-Performance Computer Architecture, Feb. 8, 2003, pp. 129-140.
Lebeck et al., “A Large, Fast Instruction Window for Tolerating Cache Misses”, IEEE Computer Society, International Conference on Computer Architecture, May 2002, pp. 59-70.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Using a modified value GPR to enhance lookahead prefetch does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Using a modified value GPR to enhance lookahead prefetch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Using a modified value GPR to enhance lookahead prefetch will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4067525

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.