Address generation interlock resolution under runahead...
Address stage logic for generating speculative address...
Apparatus and method for decreasing the latency between an...
Apparatus and method of computer program control in computer...
Branch history information writing delay using counter to...
Branch lookahead prefetch for microprocessors
Computer processor with a replay system
Computer system having an instruction for probing memory...
Concurrent execution of multiple instructions in cyclic counter
Conditional move instruction formed into one decoded...
Configurable pipeline to process an operation at alternate...
Context switching pipelined microprocessor
Control of processor pipeline movement through replay queue and
Data cache having store queue bypass for out-of-order...
Data processing apparatus
Decode and execution synchronized pipeline processing using...
Delay-slot control mechanism for microprocessors
Determining successful completion of an instruction by...
Dynamically reconfigurable stages pipelined datapath with...
Dynamically reconfigurable stages pipelined datapath with...