Address generation interlock resolution under runahead...

Details Address generation interlock resolution under runahead... Address generation interlock resolution under runahead...

2007-03-20

2007-03-20

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reducing an impact of a stall or pipeline bubble

C712S207000

Reexamination Certificate

active

10926481

ABSTRACT:
Disclosed is a method and apparatus providing a microprocessor the ability to reuse data cache content fetched during runahead execution. Said data is stored and later retrieved based upon the instruction address of an instruction which is accessing the data cache. The reuse mechanism allows the reduction of address generation interlocking scenarios with the ability to self-correct should the stored values be incorrect due to subtleties in the architected state of memory in multiprocessor systems.

REFERENCES:
patent: 5442767 (1995-08-01), Eickemeyer et al.
patent: 5915117 (1999-06-01), Ross et al.
patent: 6957304 (2005-10-01), Wilkerson
patent: 2004/0128448 (2004-07-01), Stark et al.

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