Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2007-10-09
2007-10-09
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S235000
Reexamination Certificate
active
10810235
ABSTRACT:
A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.
REFERENCES:
patent: 5165025 (1992-11-01), Lass
patent: 5717946 (1998-02-01), Satou et al.
patent: 5878252 (1999-03-01), Lynch et al.
patent: 5878254 (1999-03-01), Shimada et al.
patent: 5954815 (1999-09-01), Joshi et al.
patent: 5958047 (1999-09-01), Panwar et al.
patent: 6016532 (2000-01-01), Lynch et al.
patent: 6065115 (2000-05-01), Sharangpani et al.
patent: 6112289 (2000-08-01), Matsuo
patent: 6178492 (2001-01-01), Matsuo
patent: 6247124 (2001-06-01), Joshi et al.
patent: 6269439 (2001-07-01), Hanaki
patent: 6381678 (2002-04-01), Fu et al.
patent: 6523110 (2003-02-01), Bright et al.
Free On-Line Dictionary of Computing. FOLDOC. © 1997. www.foldoc.org search term: cache miss.
Dieffenderfer James N.
Doing Richard W.
Stempel Brian M.
Testa Steven R.
Tsuchiya Kenichi
Cockburn Joscelyn G.
Connolly Bove & Lodge & Hutz LLP
Ellis Richard L.
Li Aimee J
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