Computer processor with a replay system

Details Computer processor with a replay system Computer processor with a replay system

1998-06-30

2000-12-19

Donaghue, Larry D.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reducing an impact of a stall or pipeline bubble

712 23, 712218, G06F 1500

Patent

active

061638382

ABSTRACT:
A computer processor includes a multiplexer having a first input, a second input, and an output, and a scheduler coupled to the multiplexer first input. The processor further includes an execution unit coupled to the multiplexer output. The execution unit is adapted to receive a plurality of instructions from the multiplexer. The processor further includes a replay system coupled to the second multiplexer input and the scheduler. The replay system replays an instruction that has not correctly executed by sending a stop scheduler signal to the scheduler and sending the instruction to the multiplexer.

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patent: 5835745 (1998-11-01), Sager et al.
patent: 5966544 (1999-10-01), Sager

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