Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Patent
1997-12-19
2000-04-04
Kim, Kenneth S.
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
712244, 712245, G06F 938
Patent
active
060473703
ABSTRACT:
The invention, in one embodiment, is a processor pipeline. The pipeline includes a front end, a back end, and a queue between the front end and the back end. The queue is capable of storing an intermediate state of the processor from which the back end may be replayed. The invention, in another embodiment, is a micro-op queue storing an intermediate state of a pipeline in a processor from which a back end replay can be instituted.
REFERENCES:
patent: 5012403 (1991-04-01), Keller et al.
patent: 5428807 (1995-06-01), McKeen et al.
patent: 5659721 (1997-08-01), Shen et al.
patent: 5751985 (1998-05-01), Shen et al.
patent: 5764971 (1998-06-01), Shang et al.
patent: 5765208 (1998-06-01), Nelson et al.
patent: 5784587 (1998-07-01), Lotz et al.
patent: 5787474 (1998-07-01), Pflum
Intel Corporation
Kim Kenneth S.
LandOfFree
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