Microprocessor cache redundancy scheme using store buffer
Microprocessor with conditional cross path stall to minimize...
Multiport execution target delay queue FIFO array
Multiprocessor speculation mechanism with imprecise...
Not reported jump buffer
Operand and result forwarding between differently sized...
Operand cache addressed by the instruction address for reducing
Operand queue for use in a floating point unit to reduce...
Ordering scheme with architectural operation decomposed into...
Parallel processing of pipelined instructions having register de
Partially decoded register renamer
Pipeline data processing apparatus of reduced circuit scale
Pipelined instruction processor with data bypassing and...
Pipelined microprocessor, apparatus, and method for...
Pipelined multiply-accumulate unit and out-of-order...
Pipelined processing
Pipelined processing with commit speculation staging buffer...
Pipelined processor with microcontrol of register translation ha
Pre-arbitrated bypasssing in a speculative execution...
Preventing write-after-write data hazards by canceling...