Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2004-09-02
2011-12-20
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
Reexamination Certificate
active
08082422
ABSTRACT:
The invention includes receiving a first instruction in an in-order execution processing pipeline; starting execution of the first instruction; determining a first set of internal operation bits indicating a prospective value of control bits upon complete execution of the first instruction; determining whether the first instruction is a committed instruction; receiving a second instruction in the in-order execution processing pipeline before execution of the first instruction completes; determining a second set of internal operation bits based on: a) the first set of internal operation bits if the first instruction is a committed instruction; or b) a set of internal operation bits of a last committed instruction if the first instruction is not a committed instruction; and starting execution of the second instruction in the in-order execution processing pipeline before execution of the first instruction completes using the second internal operation bits. Numerous other aspects are provided.
REFERENCES:
John L. Hennessy, David A. Patterson; Computer Organization and Design; 1998; Second Edition; pp. 118, 368, 496-497, 500.
Chan Eddie P
Dugan & Dugan PC
International Business Machines - Corporation
Lindlof John
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