Pipelined multiply-accumulate unit and out-of-order...

Details Pipelined multiply-accumulate unit and out-of-order... Pipelined multiply-accumulate unit and out-of-order...

2007-06-12

2007-06-12

Sparks, Donald (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

C712S215000, C712S219000, C712S217000, C712S221000, C708S523000

Reexamination Certificate

active

10007498

ABSTRACT:
A mechanism for, and method of, processing multiply-accumulate instructions with out-of-order completion in a pipeline, for use in a processor having an at least four-wide instruction issue architecture, and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism including: (1) a multiply-accumulate unit (MAC) having an initial multiply stage and a subsequent accumulate stage and (2) out-of-order completion logic, associated with the MAC, that causes interim results produced by the multiply stage to be stored when the accumulate stage is unavailable and allows younger instructions to complete before the multiply-accumulate instructions.

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patent: 6112019 (2000-08-01), Chamdani et al.
Motorola, MPC7410 RISC Microprocessor Technical Summary, 2000, pp. 2-11, 20-21, 31-33, 36.
Morris, John, Computer Architecture The Anatomy of Modern Processors, 1998, http://ciips.ee.uwa.edu.au/˜morris/CA406/pipelines.html.
LSI Logic Corporation, An Overview of the ZSP Architecture White Paper, 2000.
Ruetz, Peter and Wen-Wi Ti, Interleaved Multiplier Accumulator, Sep. 12, 1992, European Patent Application.

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