Pipelined processing with commit speculation staging buffer...

Details Pipelined processing with commit speculation staging buffer... Pipelined processing with commit speculation staging buffer...

2007-03-06

2007-03-06

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

C712S244000

Reexamination Certificate

active

09564715

ABSTRACT:
A load/store centric exception handling system provided in accordance with the principles of this invention that provides a more efficient processor exception handling system wherein a speculative commit control signal (SpecComId) is generated whenever a load or store instructions is detected by the pipeline issuing unit (PIU). This speculative commit signal is sent to a Load Store Unit (LSU) which combines the SpecComID with the completed instructions in its pipeline to generate an actual commit signal (ComId) that is coupled to other processor units. Depending on what type of instructions are in the pipeline, SpecComID can be generated as early as Q stage or as late as C stage. LSU or Exc Free instructions can be speculatively committed in Q stage to move the speculative commit point up in processor pipeline. Exc Taking instructions speculatively commit in the C stage to move the speculative commit point down pipeline.

REFERENCES:
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patent: 6542988 (2003-04-01), Tremblay et al.
patent: 2002/0152259 (2002-10-01), Trong et al.

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