Parallel processing of pipelined instructions having register de

Details Parallel processing of pipelined instructions having register de Parallel processing of pipelined instructions having register de

1995-12-28

2000-07-18

Maung, Zarni

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

712215, G06F 900

Patent

active

060921846

ABSTRACT:
A method of processing instructions having register dependencies in a pipelined superscalar processor comprises the steps of fetching operands specified by a first instruction during a first pipestage, then computing address of a source operand for a second instruction so that the subsequent instruction can be processed without incurring data errors. A status bit of a destination register of the first instruction is checked during the decoding stages of the second instruction to determine whether the register is busy or free for use in performing the operation specified. In the case where the register is busy, processing of the subsequent instruction is temporarily frozen. In another situation, a result obtained by a first instruction is provided as a source operand for the second instruction so that the second instruction can be executed without delay.

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